The present invention relates to an apparatus and method for detecting a ground fault occurring on the output side of an inverter circuit.
Referring to FIG. 9, there is shown a three-phase alternating current power supply 1 grounded at a neutral point, a converter circuit, an inverter circuit, a load 9, U-, V-, and W-phase current detectors, and a ground fault detection circuit. The three-phase alternating current power supply 1 supplies current to the converter circuit, that is, the inputs of the bridged diodes 2a to 2f, which are coupled to a smoothing capacitor 3. The inverter circuit, which includes a series of switching elements 4g to 4l (e.g., IGBTs or Insulated Gate Bipolar Transistors) respectively arranged in parallel with diodes 5a to 5g, is coupled to the output of the converter circuit and capacitor 3. The diodes 5g to 5l are intended to cause a reactive current to flow in the load 9.
The output of the inverter circuit is connected to load 9 via a U-phase current detector 6, a V-phase current detector 7, and a W-phase current detector 8, which respectively output and apply a U-phase current detection signal 6a, a V-phase current detection signal 7a, and a W-phase current detection signal 8a to an adder 10. The output of the adder 10 is coupled to a comparator 11, which compares the output of the adder with a ground fault determination reference signal 12 and outputs a ground fault signal 13, accordingly.
The converter circuit is a three-phase full-wave rectifier including an R-phase composed of the diodes 2a and 2d, S-phase composed of the diodes 2b and 2e, and a T-phase composed of the diodes 2c and 2f. Likewise, the inverter circuit is a three-phase device, namely a U-phase including the switching elements 4g and 4j, V-phase including the switching elements 4h and 4k, and a W-phase including the switching elements 4i and 4l.
The current detector used with each phase is a so-called DCCT, which is a current detector employing a Hall element to detect a direct or an alternating current.
The operation of the thus constructed circuit will now be described.
An alternating current supplied by the three-phase alternating current power supply 1 is rectified by the three-phase full-wave rectifier converter circuit (i.e., the bridged diodes 2a to 2f) and is smoothed into a direct current by the capacitor 3. The smoothed direct current is applied to the switching elements 4g to 4l, which are switched ON/OFF by a gate signal from a PWM (Pulse Width Modulated) signal generator (not shown) to supply the load 9 with an alternating-current voltage of an arbitrary frequency and voltage. The PWM signal generator (e.g., a microprocessor) generates eight types of voltage vectors V0 to V7 described below.
One of the positive- and negative-arm switching elements in each phase U, V, and W is assumed to be always on. For convenience of explanation, the positive switching elements in each phase when ON are indicated as "1", and the negative switching elements when ON are indicated as "0". Accordingly, the ON/OFF states of the switching elements for the U-, V-, and W-phases are represented by a notation such as (100), (101), etc. There are eight states or phase voltage vectors V0 to V7 of the load 9 represented by (000), (001), (010), (011), (100), (101), (110), and (111). The phase voltage vectors V0 and V7 (also referred to herein as zero vectors) are voltage vectors available when the load 9 is disconnected from the inverter and the terminals are short circuited by the inverter. A signal is transmitted by the PWM signal generator to the gate of each switching element 4g to 4l to output any one of the eight voltage vectors V0 to V7.
The output frequency adjustment and output voltage control can be controlled by controlling the sequence and time of outputting the voltage vectors V0 to V7 according to a variety of processes which have already been presented and which are known in the art. Accordingly, such processes will not be described herein.
The operation of the ground fault detector circuit will now be described.
Provided that the load 9 is a three-phase balanced load, the sum of currents Iu, Iv and Iw flowing in the U-, V-, and W-phase and respectively detected by the U-phase current detector 6, the V-phase current detector 7, and the W-phase current detector 8, is zero. The U-phase current detection signal 6a, V-phase current detection signal 7a, and the W-phase current detection signal 8a are applied to the adder 10 such that if the load 9 is balanced the output of the adder 10 is zero. However, if the load is not kept balanced due to a ground fault occurring in the load, the output of the adder 10 becomes other than zero and its level is compared with the level of the ground fault determination reference signal 12 by the comparator 11. The comparator 11 will output a ground fault signal 13 if the compared level is greater than that of the ground fault determination reference signal 12. The adder 10 also serves as an absolute value amplifier.
The inverter circuit described above requires high-priced current detector DCCTs, resulting in a cost increase. In addition, the current detector DCCTs are of such a large-size that it is not practical to incorporate them into power ICs, which have become recently available on the market, and contain drive or protective circuits together with switching elements and diodes in the same package.